M24256-AWMN6T View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M24256-AWMN6T' PDF : 20 Pages View PDF
Figure 6. Write Mode Sequences with WC=0 (data write enabled)
WC
BYTE WRITE
ACK
ACK
ACK
ACK
DEV SEL
BYTE ADDR BYTE ADDR
DATA IN
R/W
M24256-A
WC
PAGE WRITE
WC (cont’d)
PAGE WRITE
(cont’d)
ACK
ACK
ACK
ACK
DEV SEL
BYTE ADDR BYTE ADDR DATA IN 1
DATA IN 2
R/W
ACK
ACK
DATA IN N
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not trig-
ger the internal write cycle.
During the internal write cycle, the SDA input is
disabled internally, and the device does not re-
spond to any requests.
AI01106B
7/20
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