M24C02-DRMF3G View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M24C02-DRMF3G' PDF : 39 Pages View PDF
Device operation
M24C02-A125
3.5
Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, as
shown in Table 2.
The device select code consists of a 4-bit device type identifier and a 3-bit Chip Enable
address (E2, E1, E0). A device select code handling any value other than 1010b (to select
the memory) or 1011b (to select the Identification page) is not acknowledged by the memory
device.
Up to eight memory devices can be connected on a single I2C bus. Each one is given a
unique 3-bit code on the Chip Enable (E2, E1, E0) inputs. When the device select code is
received, the memory device only responds if the Chip Enable Address is the same as the
value decoded on the E2, E1, E0 inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write
operations.
Table 2. Device select code
Device type identifier (1)
Chip Enable address
RW
b7
b6
b5
b4
b3
b2
b1
b0
When accessing the
memory
1
0
1
0
E2
E1
E0
RW
When accessing the
identification page
1
0
1
1
E2
E1
E0
RW
1. The most significant bit, b7, is sent first.
If the memory device does not match the device select code, it deselects itself from the bus,
and enters the Standby mode.
If the memory device matches the device select code, the corresponding memory device
gives an acknowledgment on Serial Data (SDA) during the 9th SCL clock period. Once the
memory device has acknowledged the device select code, the memory device waits for the
master to send the address byte. The memory device responds to the address byte with an
acknowledge bit.
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