M24C02-DRMF3G View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M24C02-DRMF3G' PDF : 39 Pages View PDF
M24C02-A125
4
Instructions
Instructions
4.1
Write operations
For a Write operation, the bus master sends a Start condition followed by a device select
code with the R/W bit reset to 0. The device acknowledges this, as shown in Figure 5, and
waits for the master to send the address byte with an acknowledge bit, and then waits for
the data byte.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle tW is then triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
After the successful completion of an internal Write cycle (tW), the device internal address
counter is automatically incremented to point to the next byte after the last modified byte.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 6.
DocID025755 Rev 5
15/40
39
Share Link: 
