M24C08 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M24C08' PDF : 29 Pages View PDF
M24C16, M24C08, M24C04, M24C02, M24C01
condition until the end of the address byte), the de-
vice replies to the data bytes with NoAck, as
shown in Figure 6., and the locations are not mod-
ified. After each byte is transferred, the internal
byte address counter (the 4 least significant ad-
dress bits only) is incremented. The transfer is ter-
minated by the bus master generating a Stop
condition.
Figure 7. Write Mode Sequences with WC=0 (data write enabled)
WC
BYTE WRITE
ACK
ACK
ACK
DEV SEL
BYTE ADDR
DATA IN
R/W
WC
PAGE WRITE
WC (cont'd)
PAGE WRITE
(cont'd)
ACK
ACK
ACK
ACK
DEV SEL
BYTE ADDR DATA IN 1
DATA IN 2
DATA IN 3
R/W
ACK
ACK
DATA IN N
AI02804B
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