M25P16-VMF3T View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'M25P16-VMF3T' PDF : 62 Pages View PDF
Micron M25P16 Serial Flash Embedded Memory
WRITE STATUS REGISTER
WRITE STATUS REGISTER
The WRITE STATUS REGISTER command allows new values to be written to the status
register. Before the WRITE STATUS REGISTER command can be accepted, a WRITE EN-
ABLE command must have been executed previously. After the WRITE ENABLE com-
mand has been decoded and executed, the device sets the write enable latch (WEL) bit.
The WRITE STATUS REGISTER command is entered by driving chip select (S#) LOW,
followed by the command code and the data byte on serial data input (DQ0). The
WRITE STATUS REGISTER command has no effect on b6, b5, b4, b1, and b0 of the sta-
tus register. The status register b6, b5, and b4 are always read as "0". S# must be driven
HIGH after the eighth bit of the data byte has been latched in. If not, the WRITE STATUS
REGISTER command is not executed.
Figure 14: WRITE STATUS REGISTER Command Sequence
0
C
DQ0
Command
MSB
7
8
LSB
DIN
MSB
9
DIN
10
11
DIN
DIN
12
13
14
15
LSB
DIN
DIN
DIN
DIN
DIN
As soon as S# is driven HIGH, the self-timed WRITE STATUS REGISTER cycle is initi-
ated; its duration is tW. While the WRITE STATUS REGISTER cycle is in progress, the sta-
tus register may still be read to check the value of the write in progress (WIP) bit. The
WIP bit is 1 during the self-timed WRITE STATUS REGISTER cycle, and is 0 when the
cycle is completed. Also, when the cycle is completed, the WEL bit is reset.
The WRITE STATUS REGISTER command allows the user to change the values of the
block protect bits (BP2, BP1, BP0). Setting these bit values defines the size of the area
that is to be treated as read-only, as defined in the Protected Area Sizes table.
The WRITE STATUS REGISTER command also allows the user to set and reset the status
register write disable (SRWD) bit in accordance with the write protect (W#/VPP) signal.
The SRWD bit and the W#/VPP signal allow the device to be put in the hardware protec-
ted (HPM) mode. The WRITE STATUS REGISTER command is not executed once the
HPM is entered. The options for enabling the status register protection modes are sum-
marized here.
PDF: 09005aef8456656c
m25p16.pdf - Rev. J 1/18 EN
28
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© 2011 Micron Technology, Inc. All rights reserved.
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