M25PE16
14 Revision history
Revision history
Table 24. Document revision history
Date
Revision
Changes
16-Feb-2006
0.1
Initial release.
07-Aug-2006
13-Oct-2006
20-Nov-2006
Figure 3: Bus Master and memory devices on the SPI Bus updated
and Note 2 added.
Section 4.8.1: Protocol-related protections clarified.
Address range for subsector 15 of sector 0 modified in Table 4:
Memory organization.
RESET signal behavior clarified in Section 6.5: Write Status Register
1
(WRSR), Section 6.9: Page Write (PW), Section 6.10: Page Program
(PP), Section 6.12: Page Erase (PE), Section 6.14: SubSector Erase
(SSE), Section 6.15: Bulk Erase (BE).
Section 8: Reset added to describe the device status after a RESET
Low pulse. Table Reset while a Read, Program or Erase cycle is in
progres replaced by Table 20: Timings after a RESET Low pulse
Table 19 split into two tables (see also Table 19). tBE typical value
updated. Small text changes.
HPM2 specified in HPM1 and HPM2 paragraph. Small text changes.
Table 12: Device status after a RESET Low pulse modified.
2
VIO max. modified in Table 13: Absolute maximum ratings.
fR, tW, tPW, tPP and tSSE modified in Table 18: AC characteristics.
TSL/W signal renamed as W, Top Sector Lock functionality removed,
HPM2 removed.
Paragraph added in Section 3: SPI modes. TLEAD added to Table 13:
3
Absolute maximum ratings. tTHSL and tSHTL timings removed from
Table 18: AC characteristics and Figure 26: Write Protect setup and
hold timing. SO8W package specifications updated (see Table 22
and Figure 30).
12-Apr-2007
Document status promoted from Preliminary Data to full Datasheet.
VCC supply voltage and VSS ground added. Figure 3: Bus Master
and memory devices on the SPI Bus updated, Note 2 removed and
replaced by an explanatory paragraph.
4
Behavior of WIP bit and Lock Registers specified at Power-up in
Section 7: Power-up and Power-down.
VFQFPN8 package specifications updated (see Figure 29 and
Table 21).
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