M25PX32 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M25PX32' PDF : 63 Pages View PDF
M25PX32
Instructions
Table 8.
W/VPP
signal
1
0
1
0
Protection modes
SRWD
bit
Mode
Write Protection
of the Status
Register
Memory content
Protected area(1) Unprotected area(1)
0
Status Register is
0
Writable (if the
WREN instruction
1
Software has set the WEL
protected bit)
(SPM) The values in the
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
SRWD, BP2, BP1
and BP0 bits can
be changed
Status Register is
hardware write
1
Hardware protected
protected The values in the
(HPM) SRWD, BP2, BP1
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
and BP0 bits
cannot be changed
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
Table 3
The protection features of the device are summarized in Table 8.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W/VPP) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W/VPP):
● If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.
● If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register
even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the Status Register are rejected, and are not
accepted for execution). As a consequence, all the data bytes in the memory area that
are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status
Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected mode (HPM) can be
entered:
● by setting the Status Register Write Disable (SRWD) bit after driving Write Protect
(W/VPP) Low
● or by driving Write Protect (W/VPP) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write
Protect (W/VPP) High.
If Write Protect (W/VPP) is permanently tied High, the Hardware Protected mode (HPM) can
never be activated, and only the Software Protected mode (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
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