M27V401
Table 8B. Read Mode AC Characteristics (1)
(TA = 0 to 70°C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = VCC
M27V401
Symbol Alt
Parameter
Test Condition
-180
-200
Min Max Min Max
tAVQV
tACC Address Valid to Output Valid
E = VIL, G = VIL
180
200
tELQV
tCE Chip Enable Low to Output Valid
G = VIL
180
200
tGLQV
tOE Output Enable Low to Output Valid
E = VIL
90
100
tEHQZ (2) tDF Chip Enable High to Output Hi-Z
G = VIL
0
50
0
70
tGHQZ (2) tDF Output Enable High to Output Hi-Z
E = VIL
0
50
0
70
tAXQX
tOH
Address Transition to Output
Transition
E = VIL, G = VIL
0
0
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
Unit
ns
ns
ns
ns
ns
ns
Figure 5. Read Mode AC Waveforms
A0-A18
E
G
Q0-Q7
VALID
tAVQV
tGLQV
tELQV
tAXQX
VALID
tEHQZ
tGHQZ
Hi-Z
AI00724B
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output. The associated transient voltage peaks
can be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor be used on every device between VCC
and VSS. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
used between VCC and VSS for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
6/15