Device description
2
Device description
M27W101
Note:
2.1
2.2
The operating modes of the M27W101 are listed in the Operating Modes table. A single
power supply is required in the read mode. All inputs are TTL levels except for VPP and 12V
on A9 for Electronic Signature.
Table 2. Operating modes
Mode
E
G
Read
VIL
VIL
Output Disable
VIL
VIH
Program
VIL
VIH
Verify
VIL
VIL
Program Inhibit
VIH
X
Standby
VIH
X
Electronic Signature
VIL
VIL
X = VIH or VIL, VID = 12V ± 0.5V.
P
X
X
VIL Pulse
VIH
X
X
VIH
A9
VPP
Q7-Q0
X
VCC or VSS Data Out
X
VCC or VSS
Hi-Z
X
VPP
Data In
X
VPP
Data Out
X
VPP
Hi-Z
X
VCC or VSS
Hi-Z
VID
VCC
Codes
Read mode
The M27W101 has two control functions, both of which must be logically active in order to
obtain data at the outputs. Chip Enable (E) is the power control and should be used for
device selection. Output Enable (G) is the output control and should be used to gate data to
the output pins, independent of device selection. Assuming that the addresses are stable,
the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is
available at the output after a delay of tGLQV from the falling edge of G, assuming that E has
been low and the addresses have been stable for at least tAVQV-tGLQV.
Standby mode
The M27W101 has a standby mode which reduces the supply current from 15mA to 15µA
with low voltage operation VCC ≤ 3.6V, see Read Mode DC Characteristics table for details.
The M27W101 is placed in the standby mode by applying a CMOS high signal to the E
input. When in the standby mode, the outputs are in a high impedance state, independent of
the G input.
2.3
Two-line output control
Because EPROMs are usually used in larger memory arrays, this product features a 2-line
control function which accommodates the use of multiple memory connection.
The two line control function allows:
● the lowest possible memory power dissipation,
● complete assurance that output bus contention will not occur.
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