
Summary description
M29W128FH, M29W128FL
Table 1. Signal names
DQ0-DQ7
Data Inputs/Outputs
DQ8-DQ14
Data Inputs/Outputs
DQ15A−1
Data Input/Output or Address Input
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
RB
Ready/Busy Output
BYTE
Byte/Word Organization Select
VCC
VPP/WP
VSS
NC
Supply voltage
VPP/Write Protect
Ground
Not Connected Internally
Figure 1. Logic diagram
VCC
VPP/WP
23
A0-A22
15
DQ0-DQ14
W
E
G
RP
BYTE
M29W128FH
M29W128FL
DQ15A-1
RB
VSS
AI11525
1. Also see Appendix A and Table 28 for a full listing of the Block Addresses.
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