M29W128GH70ZA1F View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
M29W128GH70ZA1F
Numonyx -> Micron
'M29W128GH70ZA1F' PDF : 94 Pages View PDF
M29W128GH, M29W128GL
3
Bus operations
Bus operations
There are five standard bus operations that control the device. These are Bus Read
(Random and Page modes), Bus Write, Output Disable, Standby and Automatic Standby.
See Table 4: Bus operations, 8-bit mode and Table 5: Bus operations, 16-bit mode for a
summary. Typical glitches of less than 5 ns on Chip Enable, Write Enable, and Reset pins
are ignored by the memory and do not affect bus operations.
3.1
Bus Read
Bus Read operations read from the memory cells, or specific registers in the command
interface. To speed up the read operation the memory array can be read in Page mode
where data is internally read and stored in a page buffer. The page has a size of 8 words (or
16 bytes) and is addressed by the address inputs A2-A0 in x 16 mode and A2-A0 plus
DQ15A−1 in byte mode.
A valid Bus Read operation involves setting the desired address on the Address inputs,
applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable
High, VIH. The Data inputs/outputs will output the value, see Figure 13: Random Read AC
waveforms (8-bit mode), Figure 15: Page Read AC waveforms (16-bit mode), and Table 26:
Read AC characteristics, for details of when the output becomes valid.
3.2
Bus Write
Bus Write operations write to the command interface. A valid Bus Write operation begins by
setting the desired address on the Address inputs. The Address inputs are latched by the
command interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data inputs/outputs are latched by the command interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH,
during the whole Bus Write operation. See Figure 16, and Figure 17, Write AC waveforms,
and Table 27 and Table 28, Write AC characteristics, for details of the timing requirements.
3.3
Output Disable
The Data inputs/outputs are in the high impedance state when Output Enable is High, VIH.
3.4
Standby
Driving Chip Enable High in Read mode, causes the memory to enter Standby mode and
the data inputs/outputs pins are placed in the high-impedance state. To reduce the Supply
current to the Standby Supply current, ICC2, Chip Enable should be held within VCC ± 0.3 V.
For the Standby current level see Table 25: DC characteristics.
During program or erase operations the memory will continue to use the Program/Erase
Supply current, ICC3, for Program or Erase operations until the operation completes.
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