M41T00S View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M41T00S' PDF : 26 Pages View PDF
Operation
Figure 7. READ mode sequence
BUS ACTIVITY:
MASTER
SDA LINE
S
WORD
ADDRESS (An)
S
BUS ACTIVITY:
SLAVE
ADDRESS
SLAVE
ADDRESS
M41T00S
DATA n
DATA n+1
DATA n+X P
AI00899
Figure 8. Alternative READ mode sequence
BUS ACTIVITY:
MASTER
SDA LINE
S
BUS ACTIVITY:
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+X P
AI00895
2.3
WRITE mode
In this mode the master transmitter transmits to the M41T00S slave receiver. Bus protocol is
shown in Figure 9. Following the START condition and slave address, a logic '0' (R/W=0) is
placed on the bus and indicates to the addressed device that word address “An” will follow
and is to be written to the on-chip address pointer. The data word to be written to the
memory is strobed in next and the internal address pointer is incremented to the next
address location on the reception of an acknowledge clock. The M41T00S slave receiver
will send an acknowledge clock to the master transmitter after it has received the slave
address see Figure 6 on page 9 and again after it has received the word address and each
data byte.
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