M41T80M View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M41T80M' PDF : 27 Pages View PDF
Operation
M41T80
2.3
WRITE mode
In this mode the master transmitter transmits to the M41T80 slave receiver. Bus protocol is
shown in Figure 10: WRITE mode sequence on page 12. Following the START condition
and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed
device that word address “An” will follow and is to be written to the on-chip address pointer.
The data word to be written to the memory is strobed in next and the internal address
pointer is incremented to the next address location on the reception of an acknowledge
clock. The M41T80 slave receiver will send an acknowledge clock to the master transmitter
after it has received the slave address see Figure 7: Slave address location on page 11 and
again after it has received the word address and each data byte.
Figure 10. WRITE mode sequence
BUS ACTIVITY:
MASTER
SDA LINE
S
WORD
ADDRESS (An)
BUS ACTIVITY:
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+X
P
AI00591
12/27
Doc ID 9074 Rev 5
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