M41T81S View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M41T81S' PDF : 29 Pages View PDF
M41T81S
Clock operation
Oscillator fail interrupt enable
If the Oscillator Fail Interrupt Bit (OFIE) is set to a '1,' the IRQ pin will also be activated. The
IRQ output is cleared by resetting the OFIE or OF Bit to '0' (not be reading the Flags
Register).
Output driver pin
Note:
When the FT Bit, AFE Bit, SQWE Bit, and Watchdog Register are not set, the
IRQ/FT/OUT/SQW pin becomes an output driver that reflects the contents of D7 of the
Calibration Register. In other words, when D7 (OUT Bit) and D6 (FT Bit) of address location
08h are a '0,' then the IRQ/FT/OUT/SQW pin will be driven low.
The IRQ/FT/OUT/SQW pin is an open drain which requires an external pull-up resistor.
Preferred initial power-on default
Upon initial application of power to the device, the following register bits are set to a '0' state:
Watchdog Register; AFE; ABE; SQWE; OFIE; and FT. The following bits are set to a '1'
state: ST; OUT; OF; and HT (see Table 5 on page 21).
Table 5. Preferred default values
Condition
ST
HT Out
FT
AFE
SQWE
ABE
WATCHDOG
Register(1)
OF
OFIE
Initial Power-up(2)
1
1
1
0
0
0
0
0
1
0
Subsequent Power-
up (with battery
UC 1 UC 0 UC UC UC
0
UC UC
back-up)(3)
1. BMB0-BMB4, RB0, RB1
2. State of other control bits undefined
3. UC = Unchanged
21/31
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