M41T82 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M41T82' PDF : 58 Pages View PDF
Operation
2
Operation
M41T82 M41T83
The M41T8x clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 32 bytes
contained in the device can then be accessed sequentially in the following order:
● 1st byte: tenths/hundredths of a second register
● 2nd byte: seconds register
● 3rd byte: minutes register
● 4th byte: century/hours register
● 5th byte: day register
● 6th byte: date register
● 7th byte: month register
● 8th byte: year register
● 9th byte: digital calibration register
● 10th byte: watchdog register
● 11th - 15th bytes: alarm 1 registers
● 16th byte: flags register
● 17th byte: timer value register
● 18th byte: timer control register
● 19th byte: analog calibration register
● 20th byte: square wave register
● 21st - 25th bytes: alarm 2 registers
● 26th - 32nd bytes: user RAM
The M41T8x clock continually monitors VCC for an out-of-tolerance condition. Should VCC
fall below VRST, the device terminates an access in progress and resets the device address
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from an out-of-tolerance system. The power input will also
be switched from the VCC pin to the battery when VCC falls below the battery back-up
switchover voltage (VSO = VRST). At this time the clock registers will be maintained by the
attached battery supply. As system power returns and VCC rises above VSO, the battery is
disconnected, and the power supply is switched to external VCC.
14/58
Share Link: 
