M41T93 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M41T93' PDF : 51 Pages View PDF
Clock operation
M41T93
3.6
Optional second programmable alarm
When the Alarm 2 Enable (AL2E) Bit (D1 of address 13h) is set to a logic ‘1,’ registers 14h
through 18h provide control for a second programmable alarm which operates in the same
manner as the alarm function described above.
The AL2E Bit defaults on initial power-up to a logic ‘0’ (Alarm 2 disabled). In this mode, the
five address bytes (14h-18h) function as additional user SRAM, for a total of 12 bytes of
user SRAM.
Figure 14. Alarm interrupt reset waveform
0Eh
0Fh
00h
ALARM FLAG BITS (AFx)
IRQ/FT/OUT
Note:
Figure 15. Back-up mode alarm waveform
VCC
VPFD
VSO
AFx Bits in Flags
Register
IRQ/FT/OUT
ABE and A1IE Bits = 1.
HIGH-Z
Table 6. Alarm repeat modes
RPT5 RPT4 RPT3 RPT2
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
0
0
0
0
0
0
0
RPT1
1
0
0
0
0
0
HIGH-Z
AI11823
trec
AI11824
Alarm setting
Once per Second
Once per Minute
Once per Hour
Once per Day
Once per Month
Once per Year
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