M41T93 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M41T93' PDF : 51 Pages View PDF
M41T93
Clock operation
3.15
Initial power-on defaults
Upon initial application of power to the device, the register bits will initially power-on in the
state indicated in Table 13 and Table 14.
Table 13. Initial power-on default values (part 1)
Condition(1)
ST
CB1 CB0 OUT FT
DCS
ACS
Digital
Calib.
Analog
Calib.
OFIE
Watchdog(2)
A1IE
SQWE ABE
Initial
0 0 0 10 0
0
0
0
0
Power-up
0
1
0
Subsequent
Power-up(3)(4)
UC
UC
UC
UC
0
UC
UC
UC UC
0
UC UC UC
1. All other control bits power-up in an undetermined state.
2. BMB0-BMB4, RB0, RB1
3. With battery back-up
4. UC = Unchanged
Table 14. Initial power-up default values (part 2)
Condition(1) RPT11-15 HT OF TE TI/TP TIE TD1 TD0 RS0 RS1-3 OTP
RPT21-
25
Initial
0
Power-up
Subsequent
Power-up (2)(3)
UC
110 0 0 1 1 1
0
0
0
1 UC 0 UC UC UC UC UC UC UC UC
1. All other control bits power-up in an undetermined state.
2. With battery back-up
3. UC = Unchanged
AL2E
0
UC
3.16
OTP bit operation (SOX18 package only)
When the OTP (One Time Programmable) Bit is set to a '1,' the value in the internal OTP
registers will be transferred to the analog calibration register (12h) and are “Read only.” The
OTP value is programmed by the manufacturer, and will contain the calibration value
necessary to achieve ±5 ppm at room temperature after two SMT reflows. This clock
accuracy can be guaranteed to drift no more than ±3 ppm the first year, and ±1 ppm for
each following year due to crystal aging.
If the OTP Bit is set to '0,' the analog calibration register will become a WRITE/READ
register and function like standard SRAM memory cells, allowing the user to implement any
desired value of analog calibration.
When the user sets the OTP Bit, they need to wait for approximately 8ms before the analog
registers transfer the value from the OTP to the analog registers due to the OTP Read
operation.
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