M48T251Y, M48T251V
Figure 7. Memory WRITE Cycle 2
WE = VIH
ADDRESSES
CE
WE
VVIIHL
tAW
VIH
tCOE
tWC
VVIIHL
VVIIHL
tWP
tWR
VIL
VIL VIH
tOEW
VIL
VIL
tODW
DQ0–DQ7
tDS
tDH
VVIIHL
DATA IN
STABLE
VVIIHL
AI04232
Note: 1. OE = VIH or VIL. If OE = VIH during a WRITE cycle, the output buffers remain in a high impedance state.
2. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high
impedance state during this period.
8/24