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M58BV016FT7T3T View Datasheet(PDF) - Numonyx -> Micron

Part Name
Description
MFG CO.
'M58BV016FT7T3T' PDF : 70 Pages View PDF
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
Bus operations
Table 7.
Bit
Burst configuration register
Description Value
Description
M15
M14
M13-M11
M10
M9
M8
M7
M6
M5-M4
M3
M2-M0
Read select
X-Latency(1)
Y-Latency(4)
Valid data ready
Burst type
Valid clock edge
Wrapping
Burst length
0 Synchronous burst read
1 Asynchronous read (default at power-on)
0 Reserved (default value)
000 Reserved (default value)
001 Reserved
010 4, 4-1-1-1(2)
011 5(3), 5-1-1-1, 5-2-2-2
100 6(3), 6-1-1-1, 6-2-2-2
101 7(3), 7-1-1-1, 7-2-2-2
110 8(3), 8-1-1-1, 8-2-2-2
111 Reserved
0 Reserved (default value)
0 One burst clock cycle (default value)
1 Two burst clock cycles
0
R valid Low during valid burst clock edge (default
value)
1 R valid Low 1 data cycle before valid burst clock edge
0 Interleaved (default value)
1 Sequential
0 Falling burst clock edge (default value)
1 Rising burst clock edge
00 Reserved (default value)
01 Reserved
10 Reserved
11 Reserved
0 Wrap (default value)
1 No wrap
000 Reserved (default value)
001 4 double-words
010 8 double-words
011 Reserved
100 Reserved
101 Reserved
110 Reserved
111 Continuous
1. X latencies can be calculated as: (tAVQV – tLLKH + tQVKH) + tSYSTEM MARGIN < (X -1) tK. (X is an integer
number from 4 to 8, tK is the clock period and tSYSTEM MARGIN is the time margin required for the
calculation).
2. This feature is available for the M58BW016F version up to the full operative frequency of 56 MHz, and for
the M58BW016D version only if the operative frequency is below 45 MHz.
3. The M58BW016F version has a maximum operative frequency of 66 MHz, fully factory tested.
4. Y latencies can be calculated as: tKHQV + tSYSTEM MARGIN + tQVKH < Y tK.
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