M7020R-083ZA1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M7020R-083ZA1' PDF : 150 Pages View PDF
M7020R
The Command Register
Table 10. Command Register Field Descriptions
Field
Range
Initial Value
Description
SRST
[0]
Software Reset. If ’1,’ this bit resets the device, with the same effect
0
as the hardware reset. Internally, it generates a reset pulse lasting for
eight CLK cycles. This bit automatically resets to a ’0’ the reset cycle
has completed.
DEVE
[1]
Device Enable. If ’0,’ it keeps the SRAM Bus (SADR, WE_L, CE_L,
OE_L, and ALE_L), SSF, and SSV signals in 3-state condition and
0
forces the cascade interface output signals LHO[1:0] and BHO[2:0] to
’0.’ It also keeps the DQ Bus in input mode. The purpose of this bit is
to make sure that there are no bus contentions when the devices
power up in the system.
TLSZ
[3:2]
Table Size. The host ASIC must program this field to configure the
chips into a table of a certain size. This field affects the pipeline
01
latency of the SEARCH and LEARN operations as well as the READ
and WRITE accesses to the SRAM (SADR[21:0], CE_L, OE_L,
WE_L, ALE_L, SSV, SSF, and ACK). Once programmed, the search
latency stays constant.
Latency in #
of CLK Cycles
TLSZ
[3:2]
00: 1 device
4
01
01: 2-8 devices
5
10: 9-31 devices
6
11: Reserved
Latency of Hit Signals. This field adds latency to the SSF and SSV
signals during SEARCH, and ACK signal during SRAM READ access
by the following number of CLK cycles.
HLAT
[6:4]
000
000: 0
001: 1
100: 4
101: 5
010: 2
110: 6
011: 3
111: 7
LDEV
[7]
Last Device in the Cascade. When set, this device is the last device
on the SRAM bus in the depth-cascaded table and is the default driver
for the SSF and SSV signals.
In the event of a SEARCH failure, the device with this bit set drives the
0
hit signals as follows:
SSF = 0, SSV = 1
During non-SEARCH cycles, the device with this bit set drives the
signals as follows:
SSF = 0, SSV = 0
LRAM
[8]
Last device on this SRAM Bus. When set, this device is the last
device on this SRAM bus in the depth-cascaded table and is the
default driver for the SADR, CE_L, WE_L, and ALE_L signals. In
cycles where no M7020R device in a depth-cascaded table drives
0
these signals, this device drives the signals as follows:
SADR = 3FFFFF,
CE_L = 1
WE_L = 1
ALE_L = 1
OE_L is always driven by the device for which this bit is set.
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