MAT02F View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'MAT02F' PDF : 12 Pages View PDF
MAT02
Transistors Q2 and Q3 form a 2 mA current source (0.65 V/
330 Ω ~ 2 mA). Each collector of Q1 operates at 1 mA. The
OP32 inputs are 3 V below the positive supply voltage (RLIC
~ 3 V). The OP32’s low input offset current, typically less than
1 nA, and low offset voltage of 1 mV cause negligible error
when referred to the amplifier input. Input stage gain is gmRL,
which is approximately 100 when operating at IC of 1 mA with
RL of 3 kΩ. Since the OP32 has a minimum open-loop gain of
500,000, total open-loop gain for the composite amplifier is
over 50 million. Even at closed-loop gain of 1000, the gain er-
ror due to finite open-loop gain will be negligible. The OP32
features excellent symmetry of slew-rate and very linear gain.
Signal distortion is minimal.
Frequency compensation is very easy with this circuit; just vary
the set-resistor RS for the desired frequency response.
Gain-bandwidth of the OP32 varies directly with the supply
current. A set resistor of 549 kΩ was found to provide the best
step response for this circuit. The resultant supply current is
found from:
( ) ( ) ( ) RSET =
V+
–
V– –
I SET
2V BE
, I SY
=15 ISET
(22)
The ISET, using ± 15 V supplies and an RSET of 549 kΩ, is ap-
proximately 52 µA which will result in supply current of 784 µA.
Dynamic range of this amplifier is excellent; the OP32 has an
output voltage swing of ± 14 V with a ± 15 V supply.
Input characteristics are outstanding. The MAT02F has offset
voltage of less than 150 µV at 25°C and a maximum offset drift
of 1 µV/°C. Nulling the offset will further reduce offset drift.
This can be accomplished by slightly unbalancing the collector
load resistors. This adjustment will reduce the drift to less than
0.1 µV/°C.
Input bias current is relatively low due to the high current gain
of the MAT02. The minimum β of 400 at 1 mA for the
MAT02F implies an input bias current of approximately 2.5 µA.
This circuit should be used with signals having relatively low
source impedance. A high source impedance will degrade offset
and noise performance.
This circuit configuration provides exceptionally low input noise
voltage and low drift. Noise can be reduced even further by rais-
ing the collector currents from 1 mA to 3 mA, but power con-
sumption is then increased.
Figure 23. Fast Logarithmic Amplifier
OUTLINE DIMENSION
Dimensions shown in inches and (mm).
6-Lead Metal Can
(TO-78)
0.185 (4.70)
0.165 (4.19)
0.040 (1.02) MAX
0.045 (1.14)
0.010 (0.25)
REFERENCE PLANE
0.750 (19.05)
0.500 (12.70)
0.250 (6.35) MIN 0.100 (2.54) BSC
0.050 (1.27) MAX
4
0.160 (4.06)
0.110 (2.79)
0.200
(5.08) 3
BSC
2
5 0.045 (1.14)
6 0.027 (0.69)
0.019 (0.48)
0.016 (0.41)
0.021 (0.53)
0.016 (0.41)
0.100
(2.54)
BSC
BASE & SEATING PLANE
1
0.034 (0.86)
0.027 (0.69)
45° BSC
Figure 24. Low-Noise, Single-Ended X1000 Amplifier
–12–
REV. C
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