MB89051PFM View Datasheet(PDF) - 3M
Part Name
Description
MFG CO.
'MB89051PFM' PDF : 40 Pages View PDF
MB89051 Series
The RP points to the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule shown next.
Rule for Conversion of Actual Addresses in the General-purpose Register Area
RP higher bits
OP code lower bits
"0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2 b1 b0
Generated address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at the time of an interrupt.
H flag
I flag
IL1, 0
: The flag is set to “1” when an arithmetic operation results in a carry from bit 3 to bit 4 or in a borrow
from bit 4 to bit 3. The bit is cleared to “0” in other instances.The flag is for decimal adjustment
instructions; do not use for other than additions and subtractions.
: Interrupt is enabled when this flag is set to “1.” Interrupt is disabled when this flag is set to “0.” The
flag is set to “0” when reset.
:
Indicates the level of the interrupt currently enabled.An interrupt is processed only if its level is
higher than the value this bit indicates.
IL1
IL0
0
0
0
1
1
0
1
1
Interrupt level
1
2
3
High-low
Higher
Lower = no interruption
N flag
Z flag
V flag
C flag
: The flag is set to “1” when an arithmetic operation results in setting of the MSB to “1” or is cleared
to “0” when the MSB is set to “1.”
: The flag is set to “1” when an arithmetic operation results in “0” or is set to “0” in other instances.
: The flag is set to “1” when an arithmetic operation results in two’s complement overflow or is
cleared to “0” if no overflow occurs.
: The flag is set to “1” when an arithmetic operation results in a carry from bit 7 or in a borrow to bit
7. The flag is cleared to “0” if neither of them occurs. In the case of a shift instruction, the flag is
set to the shift-out value.
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