MB89051 Series
(8) I2C Timing
(VCC = 5.0 V, VSS = 0 V, TA = −40 °C to +85 °C)
Parameter
Sym
bol
Pin
Value
Min
Max
Unit Remarks
Start condition output
tSTA
SCL,
SDA
1 / 4 × tinst*1 ×
mt* × nt*3 − 20
1 / 4 × tinst*1 ×
mt*2 × nt*3 + 20
ns
Master
mode
Stop condition output
tSTO
SCL,
SDA
1 / 4 × tinst*1 ×
(mt*2 × nt*3 + 8) − 20
1 / 4 × tinst*1 ×
(mt*2 × nt*3 + 8) + 20
ns
Master
mode
Start condition detect
tSTA
SCL,
SDA
1 / 4 × tinst*1 × 6 + 40
ns
Stop condition detect
tSTO
SCL,
SDA
1 / 4 × tinst*1 × 6 + 40
ns
Restart condition output
tSTASU
SCL,
SDA
1 / 4 × tinst*1 ×
(mt*2 × nt*3 + 8) − 20
1 / 4 × tinst*1 ×
(mt*2 × nt*3 + 8) + 20
ns
Master
mode
Restart condition detect
tSTASU
SCL,
SDA
1 / 4 × tinst*1 × 4 + 40
ns
SCL output Low width
tLOW SCL
1 / 4 × tinst*1 × mt*2 × nt*3
− 20
1 / 4 × tinst*1 × mt*2 × nt*3
+ 20
ns
Master
mode
SCL output High width tHIGH SCL
1 / 4 × tinst*1 ×
(mt*2 × nt*3 + 8) − 20
1 / 4 × tinst*1 ×
(mt*2 × nt*3 + 8) + 20
ns
Master
mode
SDA output delay
tDO SDA
1 / 4 × tinst*1 × 4 − 20
1 / 4 × tinst*1 × 4 + 20
ns
SDA output setup time
after interrupt
tDOSU SDA
1 / 4 × tinst*1 × 4 − 20
ns
SCL input Low pulse
width
tLOW SCL
1 / 4 × tinst*1 × 6 + 40
ns
SCL input High pulse
width
tHIGH SCL
1 / 4 × tinst*1 × 2 + 40
ns
SDA input setup time tSU SDA
40
ns
SDA hold time
tHO SDA
0
ns
*1 : For information on tinst, see “ (4) Instruction Cycle”.
*2 : m is defined in the ICCR CS 4 to CS 3 (bit 4 to bit 3) .
*3 : n is defined in the ICCR CS 2 to CS 0 (bit 2 to bit 0) .
Data transmit (master/slave)
tDO
tDO
tSU
tSU
tDOSU
SDA
SCL
tSTASU tSTA
tLOW tHO
1
ACK
9
Data receive (master/slave)
tSU
tHO
tDO
tDO
tDOSU
SDA
SCL
6
tHIGH tLOW
7
8
ACK
9
tSTO
36