MC3S12HZ256J3VAL View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MC3S12HZ256J3VAL' PDF : 692 Pages View PDF
Chapter 1 MC9S12HZ256 Device Overview
1.4.2 Signal Properties Summary
Table 1-8 summarizes all pin functions.
Table 1-8. Signal Properties
Pin
Pin
Name
Name
Function 1 Function 2
Pin
Name
Function 3
Pin
Name
Function 4
EXTAL
—
—
—
XTAL
—
—
—
RESET
—
—
—
TEST
—
—
—
XFC
—
—
—
BKGD
TAGHI
MODC
—
PAD[7:0]
AN[7:0]
KWAD[7:0]
—
PA[7:0]
PB[7:0]
PE7
FP[15:8]
FP[7:0]
FP22
ADDR[15:8]/
DATA[15:8]
ADDR[7:0]/
DATA[7:0]
XCLKS
—
—
NOACC
PE6
IPIPE1
MODB
—
PE5
IPIPE0
MODA
—
PE4
ECLK
—
—
PE3
FP21
LSTRB
TAGLO
PE2
FP20
R/W
—
PE1
IRQ
—
—
PE0
XIRQ
—
—
PK7
FP23
ECS
ROMCTL
PK[3:0]
BP[3:0] XADDR[17:14]
—
PL[7:4] FP[31:28] AN[15:12]
—
PL[3:0]
FP[19:16]
AN[11:8]
—
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VDDPLL
VDDPLL
VDDX2
VDDX2
VDDPLL
VDDX2
VDDA
VDDX1
VDDX1
VDDX1
VDDX2
VDDX2
VDDX2
VDDX1
VDDX1
VDDX2
VDDX2
VDDX1
VDDX1
VDDA
VDDX1
Internal Pull Up
Resistor
CTRL
Reset
State
Description
NA
NA Oscillator pins
NA
NA
None
None External reset pin
NA
NA Test input - must be tied to
VSS in all applications
NA
NA PLL loop Filter
Always
Up
Up Background debug, tag high,
mode pin
PERAD/ Disabled Port AD I/O, Analog inputs
PPSAD
(ATD), interrupts
PUCR
Down Port A I/O, multiplexed
address/data
PUCR
Down Port B I/O, multiplexed
address/data
PUCR
Down Port E I/O, access, clock
select, LCD driver
While RESET Port E I/O, pipe status, mode
pin is low: Down input
While RESET Port E I/O, pipe status, mode
pin is low: Down input
PUCR Down Port E I/O, bus clock output
PUCR
Down Port E I/O, LCD driver, byte
strobe, tag low
PUCR
Down Port E I/O, R/W in expanded
modes
PUCR
Up
Port E input, maskable
interrupt
PUCR
Up
Port E input, non-maskable
interrupt
PUCR
Down Port K I/O, emulation chip
select, ROM on enable
PUCR
Down Port K I/O, LCD driver,
extended addresses
PERL/
PPSL
Down Port L I/O, LCD drivers, analog
inputs (ATD)
PERL/
PPSL
Down Port L I/O, LCD drivers, analog
inputs (ATD)
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
35
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