MC68HC908AS32AVFN View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MC68HC908AS32AVFN' PDF : 280 Pages View PDF
INTERNAL DATA BUS
READ DDRB/DDRB
WRITE DDRB/DDRD
RESET
WRITE PTB/PTD
READ PTB/PTD
DDRBx/DDRDx
PTBx/PTDx
ADC DATA REGISTER
Functional Description
DISABLE
PTBx/PTDx
ADC CHANNEL x
DISABLE
INTERRUPT
LOGIC
CONVERSION
COMPLETE
AIEN
COCO
CGMXCLK
BUS CLOCK
ADC VOLTAGE IN
ADC
(ADCVIN)
ADCH[4:0]
CHANNEL
SELECT
ADC CLOCK
CLOCK
GENERATOR
ADIV[2:0] ADICLK
Figure 3-2. ADC Block Diagram
3.3.3 Conversion Time
Conversion starts after a write to the ADSCR (ADC status control register, $0038), and requires between
16 and 17 ADC clock cycles to complete. Conversion time in terms of the number of bus cycles is a
function of ADICLK select, CGMXCLK frequency, bus frequency, and ADIV prescaler bits. For example,
with a CGMXCLK frequency of 4 MHz, bus frequency of 8 MHz, and fixed ADC clock frequency of 1 MHz,
one conversion will take between 16 and 17 µs and there will be between 128 bus cycles between each
conversion. Sample rate is approximately 60 kHz.
Refer to 19.7 Analog-to-Digital Converter (ADC) Characteristics.
16 to 17 ADC Clock Cycles
Conversion Time = ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
ADC Clock Frequency
Number of Bus Cycles = Conversion Time x Bus Frequency
3.3.4 Continuous Conversion
In the continuous conversion mode, the ADC data register will be filled with new data after each
conversion. Data from the previous conversion will be overwritten whether that data has been read or not.
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
61
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