MC68HC908AS32AVFN View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MC68HC908AS32AVFN' PDF : 280 Pages View PDF
BDLC CPU Interface
4.6 BDLC CPU Interface
The CPU interface provides the interface between the CPU and the BDLC and consists of five user
registers.
• BDLC analog and roundtrip delay register (BARD)
• BDLC control register 1 (BCR1)
• BDLC control register 2 (BCR2)
• BDLC state vector register (BSVR)
• BDLC data register (BDR)
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 4-15. BDLC Block Diagram
4.6.1 BDLC Analog and Roundtrip Delay Register
This register programs the BDLC to compensate for various delays of different external transceivers. The
default delay value is16 µs. Timing adjustments from 9 µs to 24 µs in steps of 1 µs are available. The
BARD register can be written only once after each reset, after which they become read-only bits. The
register may be read at any time.
Address: $003B
Bit 7
6
5
Read:
0
ATE
RXPOL
Write:
R
4
3
2
1
Bit 0
0
BO3
BO2
BO1
BO0
R
Reset: 1
1
0
0
0
1
1
1
R = Reserved
Figure 4-16. BDLC Analog and Roundtrip Delay Register (BARD)
ATE — Analog Transceiver Enable Bit
The analog transceiver enable (ATE) bit is used to select either the on-board or an off-chip analog
transceiver.
1 = Select on-board analog transceiver
0 = Select off-chip analog transceiver
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
85
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