Electrical Characteristics
3.10.3 SPI Timing
Table 14 and Figure 19 through Figure 22 describe the timing requirements for the SPI system.
Table 14. SPI Timing
No. C
Function
Operating frequency
— D Master
Slave
SPSCK period
1 D Master
Slave
Enable lead time
2 D Master
Slave
Enable lag time
3 D Master
Slave
Clock (SPSCK) high or low time
4 D Master
Slave
Data setup time (inputs)
5 D Master
Slave
Data hold time (inputs)
6 D Master
Slave
7 D Slave access time
8 D Slave MISO disable time
Data valid (after SPSCK edge)
9 D Master
Slave
Data hold time (outputs)
10 D Master
Slave
Rise time
11 D Input
Output
Fall time
12 D Input
Output
Symbol
fop
tSPSCK
tLead
tLag
tWSPSCK
tSU
tHI
ta
tdis
tv
tHO
tRI
tRO
tFI
tFO
Min
Max
fBus/2048
0
2
4
1/2
1
1/2
1
tcyc – 30
tcyc – 30
15
15
0
25
—
—
—
—
0
0
—
—
—
—
fBus/2
fBus/4
2048
—
—
—
—
—
1024 tcyc
—
—
—
—
—
1
1
25
25
—
—
tcyc – 25
25
tcyc – 25
25
Unit
Hz
tcyc
tcyc
tSPSCK
tcyc
tSPSCK
tcyc
ns
ns
ns
ns
ns
ns
tcyc
tcyc
ns
ns
ns
ns
ns
ns
ns
ns
MC9S08QE8 Series Data Sheet, Rev. 7
22
Freescale Semiconductor