MC9S08QG4CPB View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MC9S08QG4CPB' PDF : 314 Pages View PDF
Internal Clock Source (S08ICSV1)
10.4 Functional Description
10.4.1 Operational Modes
The states of the ICS are shown as a state diagram and are described in the following sections. The arrows
indicate the allowed movements between the states.
IREFS=1
CLKS=00
FLL Bypassed
External Low
Power(FBELP)
IREFS=0
CLKS=10
BDM Disabled
and LP=1
IREFS=0
CLKS=10-
BDM Enabled
or LP =0
FLL Bypassed
External (FBE)
FLL Engaged
Internal (FEI)
FLL Engaged
External (FEE)
IREFS=0
CLKS=00
IREFS=1
CLKS=01
BDM Enabled
or LP=0
FLL Bypassed
Internal (FBI)
FLL Bypassed
Internal Low
Power(FBILP)
IREFS=1
CLKS=01
BDM Disabled
and LP=1
Entered from any state
when MCU enters stop
Stop
Returns to state that was active
before MCU entered stop, unless
RESET occurs while in stop.
Figure 10-7. Clock Switching Modes
10.4.1.1 FLL Engaged Internal (FEI)
FLL engaged internal (FEI) is the default mode of operation out of any reset and is entered when all the
following conditions occur:
• CLKS bits are written to 00
• IREFS bit is written to 1
• RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz.
In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL loop will lock the frequency to 512 times the filter frequency, as
selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the internal reference
clock is enabled.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
150
Freescale Semiconductor
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