MC9S08SF4 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MC9S08SF4' PDF : 32 Pages View PDF
AC Characteristics
3.9.1 Control Timing
Table 9. Control Timing
Parameter
Symbol
Min
Typical1
Max
Unit
Bus frequency (tcyc = 1/fBus)
External reset pulse width2
IRQ pulse width
Asynchronous path2
Synchronous path3
KBIPx pulse width
Asynchronous path2
Synchronous path3
Port rise and fall time (load = 50 pF)4
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
fBus
1
—
textrst
100
—
tILIH, tIHIL
100
1.5 tcyc
—
tILIH, tIHIL
100
1.5 tcyc
—
tRise, tFall
—
3
—
30
20
MHz
—
ns
—
ns
—
ns
—
ns
—
BKGD/MS setup time after issuing background debug force
reset to enter user or BDM modes
tMSSU
500
—
—
ns
BKGD/MS hold time after issuing background debug force
reset to enter user or BDM modes 5
tMSH
100
—
—
μs
1 Data in Typical column was characterized at 5.0 V, 25 °C.
2 This is the shortest pulse that is guaranteed to be recognized.
3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
4 Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 125°C.
5 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD.
RESET PIN
textrst
Figure 14. Reset Timing
tIHIL
IRQ/KBIPx
IRQ/KBIPx
tILIH
Figure 15. IRQ/KBIPx Timing
MC9S08SF4 Series MCU Data Sheet, Rev. 2
18
Freescale Semiconductor
Share Link: 
