MC9S12A32 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MC9S12A32' PDF : 128 Pages View PDF
MC9S12DJ64 Device User Guide — V01.20
NOTES:
1. Depending on the crystal a damping series resistor might be necessary
2. fosc = 4MHz, C = 22pF.
3. Maximum value is for extreme cases using high Q, low frequency crystals
4. Only valid if Pierce oscillator/external clock mode is selected
A.5.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.5.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
Cp
VDDPLL
Cs
R
Phase
XFC Pin
VCO
fosc
1
fref
refdv+1
∆
KΦ
KV
fvco
Detector
fcmp
Loop Divider
1
1
synr+1
2
Figure A-2 Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K1, f1 and ich from Table A-16.
The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used
for fOSC = 4MHz and a 25MHz bus clock.
The VCO Gain at the desired VCO frequency is approximated by:
KV = K1 ⋅ e-(--fK--1--1--–--⋅--f-1-v--c-V--o=--)- –100 ⋅ e(---6---–0---1--–--0---50---0--=--) -90.48MHz/V
109
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