MC9S12DB128B View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MC9S12DB128B' PDF : 128 Pages View PDF
MC9S12DT128B Device User GFurideee—sVc0a1.l0e9 Semiconductor, Inc.
2.2 Signal Properties Summary
Table 2-1 summarizes the pin functionality. Signals shown in bold are not available in the 80 pin
package.
Table 2-1 Signal Properties
Pin Name Pin Name Pin Name Pin Name Pin Name Powered
Function 1 Function 2 Function 3 Function 4 Function 5 by
Internal Pull
Resistor
CTRL
Reset
State
Description
EXTAL
—
—
—
—
VDDPLL NA
NA
Oscillator Pins
XTAL
—
—
—
—
VDDPLL NA
NA
RESET
—
—
—
—
VDDR None None External Reset
TEST
—
—
—
—
N.A.
None None Test Input
VREGEN
—
—
—
—
VDDX
NA
NA
Voltage Regulator
Enable Input
XFC
—
—
—
—
VDDPLL NA
NA PLL Loop Filter
BKGD
TAGHI
MODC
—
—
VDDR
Always
Up
Up
Background Debug,
Tag High, Mode Input
PAD[15]
AN1[7]
ETRIG1
—
Port AD Input,
—
VDDA
None
None
Analog Inputs,
External Trigger
Input (ATD1)
Port AD Input,
PAD[14:8] AN1[6:0]
—
—
—
VDDA None None Analog Inputs
(ATD1)
PAD[7]
AN0[7]
ETRIG0
—
Port AD Input, Analog
—
VDDA None None Inputs, External
Trigger Input (ATD0)
PAD[6:0] AN0[6:0]
—
—
—
VDDA
None
None
Port AD Input, Analog
Inputs (ATD0)
PA[7:0]
ADDR[15:8]/
DATA[15:8]
—
—
—
VDDR
PUCR/
PUPAE
Port A I/O,
Disabled Multiplexed
Address/Data
PB[7:0]
ADDR[7:0]/
DATA[7:0]
—
—
—
VDDR
PUCR/
PUPBE
Disabled
Port B I/O,
Multiplexed
Address/Data
PE7
NOACC
XCLKS
—
—
VDDR
PUCR/
PUPEE
Up
Port E I/O, Access,
Clock Select
PE6
IPIPE1
MODB
—
PE5
IPIPE0
MODA
—
—
VDDR
Port E I/O, Pipe
While RESET pin Status, Mode Input
low:
—
VDDR
Down
Port E I/O, Pipe
Status, Mode Input
PE4
ECLK
—
—
—
VDDR
PUCR/
PUPEE
Up
Port E I/O, Bus Clock
Output
PE3
LSTRB
TAGLO
—
—
VDDR
PUCR/
PUPEE
Up
Port E I/O, Byte
Strobe, Tag Low
PE2
R/W
—
—
—
VDDR
PUCR/
PUPEE
Up
Port E I/O, R/W in
expanded modes
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