MC9S12DG128 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MC9S12DG128' PDF : 142 Pages View PDF
Device User Guide — 9S12DT128DGV2/D V02.16
Cp
VDDPLL
Cs
R
Phase
XFC Pin
VCO
fosc
1
fref
refdv+1
∆
KΦ
KV
fvco
Detector
fcmp
Loop Divider
1
1
synr+1
2
Figure A-3 Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K1, f1 and ich from (Table A-16).
The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used
for fOSC = 4MHz and a 25MHz bus clock.
The VCO Gain at the desired VCO frequency is approximated by:
KV = K1 ⋅ e-(--fK--1--1--–--⋅--f-1-v--c-V--o=---) –100 ⋅ e(---6---–0---1--–--0---50---0--=--) -90.48MHz/V
The phase detector relationship is given by:
KΦ = – ich ⋅ KV
= 316.7Hz/Ω
ich is the current in tracking mode.
The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.
fC < ----------2-----⋅---ζ----⋅---f--r--e---f----------
π ⋅ ⎝⎛ζ + 1 + ζ2⎠⎞
1--1--0-- → fC < 4----f-⋅r--e-1---f-0- ;(ζ
fC < 25kHz
= 0.9)
122
Freescale Semiconductor
Share Link: 
