MC9S12DG256B View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
MC9S12DG256B
Freescale Semiconductor
'MC9S12DG256B' PDF : 126 Pages View PDF
MC9S12DP256B Device User GFuirdeee—scV0a2.l1e5 Semiconductor, Inc.
The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.
fC < ----------2-----⋅---ζ----⋅---f--r--e----f---------
π ⋅ ζ + 1 + ζ2
5--1--0-- → fC < 4----f-⋅r--e-5---f-0- ;(ζ = 0.9)
And finally the frequency relationship is defined as
n = -f-V-f--r-C-e---fO--- = 2 ⋅ (synr + 1)
With the above inputs the resistance can be calculated as:
R = 2-----⋅---π---K--⋅--Φ-n-----⋅---f--C--
The capacitance Cs can now be calculated as:
Cs = -π----2⋅---f--⋅C---ζ--⋅-2--R--- ≈ 0-f--C-.--5--⋅-1--R-6--;(ζ = 0.9)
The capacitance Cp should be chosen in the range of:
Cs ⁄ 20 ≤ Cp ≤ Cs ⁄ 10
The stabilization delays shown in Table A-16 are dependant on PLL operational settings and external
component selection (e.g. crystal, XFC filter).
A.5.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock fcmp, the
deviation from the reference clock fref is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.
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