MC9S12DT512 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MC9S12DT512' PDF : 124 Pages View PDF
MC9S12DP512 Device Guide V01.25
Section 6 HCS12 Core Block Description
6.1 CPU12 Block Description
Consult the HCS12 CPU Reference Manual for information on the CPU.
6.1.1 Device-specific information
When the HCS12 CPU Reference Manual refers to cycles this is equivalent to Bus Clock periods.
So 1 cycle is equivalent to 1 Bus Clock period.
6.2 HCS12 Module Mapping Control (MMC) Block Description
Consult the MMC Block Guide for information on the HCS12 Module Mapping Control module.
6.2.1 Device-specific information
• INITEE
– Reset state: $01
– Bits EE11-EE15 are "Write once in Normal and Emulation modes and write anytime in Special
modes".
• PPAGE
– Reset state: $00
– Register is "Write anytime in all modes"
6.3 HCS12 Multiplexed External Bus Interface (MEBI) Block
Description
Consult the MEBI Block Guide for information on HCS12 Multiplexed External Bus Interface module.
6.3.1 Device-specific information
• PUCR
– Reset state: $90
6.4 HCS12 Interrupt (INT) Block Description
Consult the INT Block Guide for information on the HCS12 Interrupt module.
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