MC9S12DT512VFU View Datasheet(PDF) - Freescale Semiconductor

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Description

MFG CO.

MC9S12DT512VFU

MC9S12DP512 Device Guide V01.25

Freescale Semiconductor 

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MC9S12DP512 Device Guide V01.25

SS

(INPUT)

SCK

(CPOL = 0)

(INPUT)

SCK

(CPOL = 1)

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

1

2

4

4

9

see

note

SLAVE

MSB OUT

7

5

6

MSB IN

NOTE: Not defined!

12

12

11

BIT 6 . . . 1

BIT 6 . . . 1

3

13

13

8

SLAVE LSB OUT

LSB IN

Figure A-9 SPI Slave Timing (CPHA=1)

In Table A-20 the timing characteristics for slave mode are listed.

Table A-20 SPI Slave Mode Timing Characteristics

Num

Characteristic

Symbol

Min

1 SCK Frequency

fsck

DC

1 SCK Period

tsck

4

2 Enable Lead Time

tlead

4

3 Enable Lag Time

tlag

4

4 Clock (SCK) High or Low Time

twsck

4

5 Data Setup Time (Inputs)

tsu

8

6 Data Hold Time (Inputs)

thi

8

7 Slave Access Time (time to data active)

ta

—

8 Slave MISO Disable Time

tdis

—

9 Data Valid after SCK Edge

tvsck

—

10 Data Valid after SS fall

tvss

—

11 Data Hold Time (Outputs)

12 Rise and Fall Time Inputs

13 Rise and Fall Time Outputs

tho

20

trfi

—

trfo

—

NOTES:

1. tbus added due to internal synchronization delay

Typ

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Max

1/4

∞

—

—

—

—

—

20

22

30 + tbus 1

30 + tbus 1

—

8

8

Unit

fbus

tbus

tbus

tbus

tbus

ns

ns

ns

ns

ns

ns

ns

ns

ns

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