Freescale SemiconDdevuiccetUoserr,GIunidce.— 9S12E128DGV1/D V01.04
Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and
interrupts. System resets can be generated through external control of the RESET pin, through the clock
and reset generator module CRG or through the low voltage reset (LVR) generator of the voltage regulator
module. Refer to the CRG and VREG Block Guides for detailed information on reset generation.
5.2 Vectors
Table 5-1 lists interrupt sources and vectors in default order of priority.
Vector Address
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFE8 to $FFEF
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFDE, $FFDF
$FFDC, $FFDD
$FFDA, $FFDB
$FFD8, $FFD9
$FFD6, $FFD7
$FFD4, $FFD5
$FFD2, $FFD3
$FFD0, $FFD1
$FFCE, $FFCF
$FFC8 to $FFCD
$FFC6, $FFC7
$FFC4, $FFC5
Table 5-1 Interrupt Vector Locations
Interrupt Source
CCR
Mask
Local Enable
External Reset, Power On Reset or Low
Voltage Reset (see CRG Flags Register None
to determine reset source)
None
Clock Monitor fail reset
None COPCTL (CME, FCME)
COP failure reset
None
COP rate select
Unimplemented instruction trap
None
None
SWI
None
None
XIRQ
X-Bit
None
IRQ
I-Bit
INTCR (IRQEN)
Real Time Interrupt
I-Bit
CRGINT (RTIE)
Reserved
Standard Timer 0 channel 4
I-Bit
TIE (C4I)
Standard Timer 0 channel 5
I-Bit
TIE (C5I)
Standard Timer 0 channel 6
I-Bit
TIE (C6I)
Standard Timer 0 channel 7
I-Bit
TIE (C7I)
Standard Timer overflow
I-Bit
TSCR2 (TOI)
Pulse accumulator overflow
I-Bit
PACTL(PAOVI)
Pulse accumulator input edge
I-Bit
PACTL (PAI)
SPI
I-Bit
SPICR1 (SPIE, SPTIE)
SCI0
I-Bit
SCICR2
(TIE, TCIE, RIE, ILIE)
SCI1
I-Bit
SCICR2
(TIE, TCIE, RIE, ILIE)
SCI2
I-Bit
SCICR2
(TIE, TCIE, RIE, ILIE)
ATD
I-Bit
ATDCTL2 (ASCIE)
Port AD (KWU)
I-Bit
PTADIF (PTADIE)
Reserved
CRG PLL lock
I-Bit
PLLCR (LOCKIE)
CRG Self Clock Mode
I-Bit
PLLCR (SCMIE)
HPRIO Value
to Elevate
–
–
–
–
–
–
$F2
$F0
$E6
$E4
$E2
$E0
$DE
$DC
$DA
$D8
$D6
$D4
$D2
$D0
$CE
$C6
$C4
95
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