MCF51QH128 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MCF51QH128' PDF : 68 Pages View PDF
Nonswitching electrical specifications
Table 9. EGPIO General Control Timing (continued)
Symbol
Description
GPIO pin interrupt pulse width (digital glitch filter disabled,
analog filter disabled)
Asynchronous path2
External reset pulse width (digital glitch filter disabled)
Mode select (MS) hold time after reset deassertion
Min.
50
100
2
Max.
—
—
—
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
Unit
ns
ns
Bus
clock
cycles
Bus clock
Data outputs
Data inputs
G1
G2
G3
G4
Figure 3. EGPIO timing diagram
The following general purpose specifications apply to all signals configured for RGPIO,
FTM, and UART. The conditions are 25 pf load, VDD = 3.6 V to 1.71 V, and full
temperature range. The GPIO are set for high drive, no slew rate control, and no input
filter, digital or analog, unless otherwise specified.
Table 10. RGPIO General Control Timing
Symbol
Description
R1
CPUCLK from CLK_OUT pin high to GPIO output valid
R2
CPUCLK from CLK_OUT pin high to GPIO output invalid
(output hold)
R3
GPIO input valid to bus clock high
R4
CPUCLK from CLK_OUT pin high to GPIO input invalid
Min.
—
1
17
—
Max.
16
—
—
2
Unit
ns
ns
ns
ns
MCF51QH128 Advance Information Data Sheet, Rev. 0, 05/2011.
18
Preliminary
Freescale Semiconductor, Inc.
Share Link: 
