MCP1726 View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'MCP1726' PDF : 30 Pages View PDF
MCP1726
Junction Temperature Estimate
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below:
TJ = TJRISE + TA(MAX)
TJ = 48.8°C + 70.0°C
TJ = 118.8°C
As you can see from the result, this application will be
operating very near the maximum operating junction
temperature of 125°C. The PCB layout for this
application is very important as it has a significant
impact on the junction-to-ambient thermal resistance
(RθJA) of the 3x3 DFN package, which is very important
in this application.
Maximum Package Power Dissipation at
70°C Ambient Temperature
3x3 DFN (41° C/W RθJA)
PD(MAX) = (125°C – 70°C) / 41° C/W
PD(MAX) = 1.34W
8LD SOIC (150°C/Watt RθJA)
PD(MAX) = (125°C – 70°C)/ 150° C/W
PD(MAX) = 0.366W
From this table you can see the difference in maximum
allowable power dissipation between the 3x3 DFN
package and the 8-pin SOIC package. This difference
is due to the exposed metal tab on the bottom of the
DFN package. The exposed tab of the DFN package
provides a very good thermal path from the die of the
LDO to the PCB. The PCB then acts like a heatsink,
providing more area to distribute the heat generated by
the LDO.
DS21936C-page 20
© 2007 Microchip Technology Inc.
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