MFRC52201HN1/TRAYB View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'MFRC52201HN1/TRAYB' PDF : 95 Pages View PDF
NXP Semiconductors
MFRC522
Standard performance MIFARE and NTAG frontend
6. Block diagram
The analog interface handles the modulation and demodulation of the analog signals.
The contactless UART manages the protocol requirements for the communication
protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data
transfer to and from the host and the contactless UART and vice versa.
Various host interfaces are implemented to meet different customer requirements.
ANTENNA
ANALOG
INTERFACE
CONTACTLESS
UART
FIFO
BUFFER
Fig 1. Simplified block diagram of the MFRC522
REGISTER BANK
SERIAL UART
SPI
I2C-BUS
HOST
001aaj627
MFRC522
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.9 — 27 April 2016
112139
© NXP Semiconductors N.V. 2016. All rights reserved.
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