MK68564 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'MK68564' PDF : 46 Pages View PDF
MK68564
D4, D3 : Receive Interrupt Modes 1 and 0
Together, these two bits specify the various charac-
ter-avalaible conditions that will cause interrupt re-
quests. When receiver interrupts are enabled, a
Special Receive Condition can cause an interrupt
request and modify the interrupt vector. Special Re-
ceive conditions are : Rx Overrun Error, Framing Er-
ror (in async mode), End Of Frame (in SDLC mode),
and Parity Error (when selected). The Rx Overrun
Error and the Parity Error conditions are latched in
Status Register 1 when they occur ; they are cleared
by an Error Reset command (Command 4) or by a
hardware or channel rest.
Rx INT Rx INT
MODE 1 MODE 0
0
0
Receive Interrupts Disabled
0
1
Receive Interrupt On First
Character Only
1
0
Interrupt On All Receive
Characters-parity
Error is a Special Receive
Conditi on
1
1
Interrupt On All Receive
Characters-parity
Error is not a Special Receive
Conditi on
Receive Interrupts Disabled. This mode prevents
the receiver from generating an interrupt request
and clears any pending receiver interrupts. If a char-
acter is avalaible in the receiver data FIFO, or if a
Special Receive Condition exists before or during
the time receiver interrupts are disabled, and recei-
ver interrupts are then enabled without clearing
these conditions, an interrupt request will immedi-
ately be generated.
Receive Interrupt On First Character Only. The
receiver requests an interrupt in this mode on the
first available character (or stored FIFO character),
or on a Special Receive Condition. If a Special Re-
ceive Condition occurs, the data with the special
condition is held in the receive data FIFO until an Er-
ror Reset command (Command 6) is issued.
The receive Interrupt On First Character Only mode
can be re-enabled by the Enable Interrupt On Next
Rx Character command (Command 4). If this inter-
rupt mode was terminated by a Special Receive
Condition, the Error Reset command must be is-
sued, before Command 4, for proper operation to re-
sume.
Interrupt On All Receive Characters. This mode
ammows an interrupt for every character received
(or character in the receive data FIFO) and provides
a unique vector (if Status Affects ector is enabled)
when a Special Receive Condition exists. When the
interrupt request is due to a special condition, the
data containing that condition, the data containing
data FIFO.
D2 : Status Affects Vector
When this bit is zero, the value programmed into the
Vector Register is returned during a read cycle or an
interrupt acknowledge cycle. If the Vector Register
has not been programmed following a hardware re-
set, then ”0FH” is returned.
When this bit is a one, the vector returned during a
read cycle or an interrupt acknowledge cycle is va-
riable. The variable field returned depends on the hi-
ghest-priority pending interrupt at the start of the cy-
cle.
The Status Affects Vector control bits from both
channels are logical ”or” ed together ; therefore, if ei-
ther is programmed to a one, its operation affects
both channels. This is the only control bit that func-
tions in this manner on the MK68564.
V2 V1 0
Interrupt Condition
0 0 0 Ch B Transmit Buffer Empty
0 0 1 Ch B External/status Change
0 1 0 Ch B Receive Character Available
0 1 1 Ch B Special Receive Condition*
1 0 0 Ch A Transmit Buffer Empty
1 0 1 Ch A External/status Change
1 1 0 Ch A Receive Character Available
1 1 1 Ch A Special Receive Condition*
* Speci al Receive Condi ti ons : Parity Error, Rx Overrun Er-
D1 : Transmit Interrupt Enable
When this bit is set to a one, the transmitter will re-
quest an interrupt whenever the transmit buffer be-
comes empty. When this bit is zero, no transmitter
interrupts will be requested.
D0 : External/Status Interrupt Enable
When this bit is set to a one, an interrupt will be re-
quested by the external/status logic on any of the fol-
lowing occurrences : a transition (high-to-low or low-
to-high) on the DCD, CTS, or SYNC input pins, a
break/abort condition that has been detected and
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