MK74ZD133F View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'MK74ZD133F' PDF : 8 Pages View PDF
PRELIMINARY INFORMATION
MK74ZD133
PLL and 32-Output Clock Driver
Output Frequency Select Table
Output Frequency Generation
Address S4 S3 S2 S1 S0
0
00000
1
00001
2
00010
3
00011
4
00100
5
00101
6
00110
7
00111
8
01000
9
01001
10
01010
11
01011
12
01100
13
01101
14
01110
15
01111
16
10000
17
10001
18
10010
19
10011
20
10100
21
10101
22
10110
23
10111
24
11000
25
11001
26
11010
27
11011
28
11100
29
11101
30
11110
31
11111
Input (F)
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
7 - 26.5
3 - 10
4 - 13.33
5 - 16
reserved
10 - 40
6 - 20
20 - 80
Input (Y)
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
7 - 44.44
3 - 16.67
4 - 22.22
5 - 26.67
reserved
10 - 66.67
6 - 33.33
20 - 100
Output
90*
30
81*
25
54
50
33.33
27
64
75
83.33*
66.66
133.33*
62.5
31.25
125*
55
53.125
135*
106.25*
106*
106.25*
106.66*
107*
x3
x8
x6
x5
reserved
x2
x4
x1
The MK74ZD133 has two primary
modes of operation: “Clock Generator”
and “Zero Delay Multiplier”.
In Clock Generator mode, addresses 0
through 23, specific output frequencies
are generated from a 20 MHz input.
There is no fixed phase relationship
between the input and output clocks.
In Zero Delay Multiplier mode,
addresses 24 through 31, the output
frequency is a simple integer multiple of
the input. The input range can vary over
several MHz, making it possible to
generate output frequencies that are not
included in Clock Generator mode. In
this mode, FBOUT3 is fed back to the
FBIN pin, and the rising edges of the
input and outputs are synchronized.
Configuring the Input/Output
Pins
The MK74ZD133 uses I/O pins whose
status as select inputs are sampled upon
power-up. The chip then selects this
address in the table to the left, and stays
in that configuration until a new power-
up sequence, when the select inputs are
sampled again. These pins all have
internal pull-up resistors, so the 10kΩ
resistor is only needed to connect to
ground for the 0 selection in the table
(as shown below).
* These modes only guaranteed in the Y (LQFP) package
For select
= 0 (low)
33Ω
I/O
to load
10kΩ
Don’t stuff 10k
for“1” selection
MDS 74ZD133 C
5
Revision 010899
Printed 11/17/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com
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