ML2712EH View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
MFG CO.
'ML2712EH' PDF : 22 Pages View PDF
PRELIMINARY
ML2712
CONTROL INTERFACES (CONTINUED)
SERIAL CONTROL BUS
The ML2712 contains two 3-wire serial control
interfaces. They have common clock and data, but
separate latch enable controls (EN & DACEN). The EN
signal programs the registers that determine the
operation of the PLLs, VCOs and DAC, and
determines which circuits are active in STANDBY,
RECEIVE and TRANSMIT Modes. The DACEN signal is
dedicated to DAC programming only. Serial bus
control is active in all operating Modes. The serial
control interface overrides the parallel mode control
interface. See Table 2 and Figure 9.
All DATA bits are clocked into the ML2712 while EN
or DACEN is low and loaded into the addressed latch
on the low to high trailing edge of the EN or DACEN
pulse. The serial bus control register only retains the
last 16 bits of data that follow either the EN or DACEN
pulse. The data latches are fully static CMOS and use
minimal power when the Serial Control Bus is inactive.
All Serial Control Bus words are entered data MSB first.
The word is made up of data and address fields. The data
field is the leading 13 bits and the last 3 bits are the
address field (see Table 3). The address field determines
the destination register for the data field. There are 5
control registers (CONTROL WORDs A, B, C, D, and E)
defined in Table 4. When data is latched by a DACEN
pulse the address field is ignored and the data field is
always used to program the 8-bit DAC. In Tables 3 and 4
the left-most bit isalways the MSB.
EN or DACEN are enabled to latch data into the DAC
register as determined by the DCE control bit, b4 in
Control Word B. When DCE is set to 0, the default
power up state, the EN latch enable pulse is active
and the DACEN pulse is disabled. In this state a rising
edge on EN will write data to the 8-bit DAC when the
address field is correct. Other control words may be
written using different address fields as shown in
Table 4. When DCE is set to 1 both DACEN and EN
pulses are active and either may be used to latch
control words, although not simultaneously. In this
mode DACEN will write data to the 8-bit DAC
regardless of the address data. The EN pulse will
continue to operate as described for DCE set to 0.
The ML2712 default power up condition is designed
for normal operation. At power up the registers are
programmed as in Table 4. The user may adjust the
mode of operation for specific tasks by programming
the control register settings immediately after power
up, or at an appropriate time during operation. Note
that address field 000 is reserved for test modes and
should not be programmed in normal operation.
tS
tR
tH
tF
tCK
tL
CLK
DATA
MSB
EN &
DACEN
tSE
tEW
Figure 9. Control Bus Timing
Parameter
Min Typ Max Units
CLK
tR
tF
tCK
EN & DACEN
Rise time
Fall time
Period
15
ns
15
ns
50
ns
tEW
Pulse width
2
ns
tL
Falling edge delay
15
ns
tSE
Rising edge setup
15
ns
DATA
tS
Data-to-Clock Setup 15
ns
tH
Data-to-Clock Hold
15
ns
Table 2. Three Wire Bus Interface Timing Characteristics
Field
bit
Function
DATA
ADDRESS
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14 15
Data Data Data Data Data Data Data Data Data Data Data Data Data Add Add Add
12
11 10
9
8
7
6
5
4
3
2
1
0
3
2
1
Table 3. Format of Serial Control Bus data
January, 2000 PRELIMINARY DATASHEET
13
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