ML2721 View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
MFG CO.
'ML2721' PDF : 27 Pages View PDF
PRELIMINARY
CONTROL INTERFACES
ML2721
There are two control interfaces:
Parallel mode control. Controlling the mode of
operation of the ML2721. Refer to the Operational
Modes section for details.
Serial Interface. Programing the PLL signal and
reference dividers, internal test modes, and filter
alignment.
Other signal interfaces to the IC are:
n Receiver data output
n Transmit modulation data input
n PLL lock detect output, to indicate when the on chip
PLL is in frequency lock
n Receive RF input, the input to the receiver circuits
n Transmit RF output, the output for the modulated RF
signal
n Received signal strength output: RSSI indicates the
power of the received signal
n Reference frequency input for PLL dividers
Bit Allocations
Data words are entered beginning with the MSB. The word
is divided into a leading 14-bit data field and a 2-bit
address field. When the address field has been decoded
the destination register is loaded on the rising edge of EN.
Providing less than 16 bits of data will result in
unpredictable behavior when EN goes high.
Parallel Interface
The chip is enabled by the XCEN (Transceiver enable)
signal. The operating mode is set by the two control lines
TX/RX (Transmit/Receive Mode) and PLLEN (PLL enable),
and the 3 wire serial data bus. The logic for XCEN, RXON
and PLLEN is given in Table 7.
XCEN
0
1
1
1
1
RXON
X
0
0
1
1
PLLEN
X
1
0
1
0
Mode Name
Off
TXCAL
TX
RXCAL
RX
Chip Mode
Off
Transmit synthesizer closed loop
Transmit synthesizer open loop and modulated
Receive synthesizer closed loop and filter align
Receive on
Table 7. Control Logic
16
PRELIMINARY DATASHEET January, 2000
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