ML2721 View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
MFG CO.
'ML2721' PDF : 27 Pages View PDF
APPLICATIONS
PRELIMINARY
The ML2721 operates in the 902 to 928MHz ISM band
under FCC Part 15, section 247 or section 249. For
Cordless telephone applications under part FCC 15
section 247 the ML2721 and its companion part (ML2751
or ML2752) are used as a Direct Sequence Spread
Spectrum (DSSS) transceiver with chip rates up to
1.6Mchips/s. The ML2721 is used alone for short range
high data rate applications under FCC Part 15 section 249.
DSSS CORDLESS TELEPHONE
The ML2721 requires a suitable digital baseband processor
to operate in this mode. The baseband processor spreads
the digital data (at up to 150kbytes/s) using an 11 to 15
bit chip sequence. This composite baseband signal (at up
to 1.6Mchips/s) is fed to the ML2721 DIN input. The
ML2721 transmit circuits low pass filter the baseband
signal and FM modulate the transmit RF output. The
transmitted signal is a Direct Sequence-FSK signal which
meets the FCC requirements for >10dB processing gain
and a 6dB bandwidth >500kHz. It is a constant envelope
signal which can be amplified in an efficient Class C
power amplifier without suffering spectral regrowth. The
ML2721 receive circuits downconvert, filter, and
demodulate the FM signal to recover the original spread
spectrum baseband signal. The baseband processor de-
spreads this signal and recovers the lower data rate signal
with a correlator. To extend the range in this DS-FSK
mode the companion ML2751 (or ML2752) part is used.
This is a combination transmit power amplifier, receive
low noise amplifier, and PIN diode driver for 902 to
928MHz ISM band applications.
LOW POWER STAND ALONE
The ML2721 can be used without the ML2751/2 as an FSK
radio transceiver. Only an external PIN diode T/R switch
and antenna filtering are required. The 0dBm (typical)
output makes full use of the FCC Part 15, section 247 or
section 249 transmitted field strength limits. Bit rates
from1.0 to1.6Mbits/s are feasible. The data slicer achieves
full performance with run lengths up to 4 consecutive 1 or
0 bits at 1.3 to 1.6Mbits/s (3 consecutive bits at 1Mbit/s).
This constraint can be met with run length limited coding,
which also simplifies the clock recovery circuits.
Alternatively an external data slicer circuit can be used
for longer run lengths.
ML2721
January, 2000 PRELIMINARY DATASHEET
23
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