ML2722DH View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
MFG CO.
'ML2722DH' PDF : 28 Pages View PDF
DATA BIT
B15 (MSB) / DB13
B14 / DB12
B13 / DB11
B12 / DB10
B11 / DB9
B10 / DB8
B9 / DB7
B8 / DB6
B7 / DB5
B6 / DB4
B5 / DB3
B4 / DB2
B3 / DB1
B2 / DB0
B1 / ADB1
B0 (LSB) / ADB0
DATA BIT
B15 (MSB) / DB13
B14 / DB12
B13 / DB11
B12 / DB10
B11 / DB9
B10 / DB8
B9 / DB7
B8 / DB6
B7 / DB5
B6 / DB4
B5 / DB3
B4 / DB2
B3 / DB1
B2 / DB0
B1 / ADB1
B0 (LSB) / ADB0
ML2722
NAME
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TPC
TXCL
LOL
RXCL
RD0
QPP
ADR1
ADR0
NAME
Reserved
Reserved
CHQ11
CHQ10
CHQ9
CHQ8
CHQ7
CHQ6
CHQ5
CHQ4
CHQ3
CHQ2
CHQ1
CHQ0
ADR1
ADR0
DESCRIPTION
USE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Transmit Power Control
Transmit Test Mode
PLL Frequency Shift
PLL Mode in Normal Receive
Operation
Reference Frequency Select
PLL Charge Pump Polarity
MSB Address Bit
LSB Address Bit
Set all bits to 0 (zero)
0: TPC pin high impedance
1: TPC pin pulled to ground
0: FSK modulation in Transmit mode
1: CW (no modulation in Transmit mode)
0: LO shift is 0 Hz for Transmit, 1.024MHz for Receive
1: LO shift is 1.024MHz for Transmit, 0Hz for Receive
0: PLL open loop during Receive
1: PLL closed loop during Receive
0: 6.144MHz nominal reference frequency
1: 12.288MHz nominal reference frequency
0: Freq. sig. < freq. ref.; Charge pump sources current
1: Freq. sig. < freq. ref.; Charge pump sinks current
ADR1 = 0
ADR0 = 0
Table 4. Register 0 -- PLL Configuration Register
DESCRIPTION
USE
Set all bits to 0 (zero)
Channel Frequency select bits
Divide ratio = fc / 0.512
MSB Address Bit
LSB Address Bit
ADR1 = 0
ADR0 = 1
Table 5. Register 1 – Channel Frequency Register
DS2722-F-06
FINAL DATASHEET
DECEMBER 2005 21
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