ML2724 View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
MFG CO.
'ML2724' PDF : 26 Pages View PDF
ML2724
LVLO - Register 0, Bit 10
Low Voltage Lock Out: The LVLO bit enables a transmit low voltage lockout latch, which shuts off the transmitter by
de-asserting the PAON output. This latch is set if the supply voltage drops below 2.65V and is reset when the RXON
control input goes high (see Table 12).
LVLO
PAON BEHAVIOR
0
PAON Undisturbed
1 PAON de-asserted when VCCA<2.65V,
Reset by RXON high.
Table 12: LVLO Operation
RCLP - Register 0, Bit 11
RSSI Clip Enable: The RCLP bit disables the RSSI clipping circuitry. With RCLP low, the RSSI output voltage is
clipped to a maximum of about 2.0V at –10dBm. With RCLP high, the RSSI is not clipped. (see Table 13).
RCLP
RSSI BEHAVIOR
0 RSSI output clipped to a maximum of ~1.9V at –15dBm
1 RSSI output not clipped
Table 13: RCLP Operation
CHQ <11:0> - Register 1, Bits 2-13
Channel Frequency Selection: These bits set the RF carrier frequency for the transceiver (see Table 14). With a
6.144MHz or 12.288MHz clock at the FREF pin, the channel frequency value is calculated by multiplying the CHQ value
by 1.024. The recommended operating range value of the CHQ is from 2,346 to 2,424. These bits must be
programmed to a valid channel frequency before XCEN is asserted.
B15 B14
B13 TO B2
B1 B0
0 0 CHQ - PLL Divide Ratio 0 1
Table 14: Main Divider
The divide ratio is calculated as fC /1.024 where fC is the channel frequency in MHz.
fC=1.024 * CHQ
DS2724-F-03
FINAL DATASHEET
DECEMBER 2005 21
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