ML4411A View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
MFG CO.
'ML4411A' PDF : 14 Pages View PDF
BRAKING
As shown in figure 9, the braking circuit pulls the N-
Channel MOSFET gates high when BRAKE falls below a
1.4V threshold. After a power failure, CDLY is discharged
slowly through RDLY providing a delay for retract to occur
before the braking circuit is activated. The N-Channel
buffer (B1) tri-states when the BRAKE pin reaches 2.1V to
ensure that no charge from CBRK is lost through the pull-
down transistor in B1. To brake the motor with external
signals, first disable power by pulling pin 8 low, then pull
pin 26 below 1.4V using an open drain (or diode isolated)
output.
The bias current for the Braking circuits comes from
VCC2. When the N-Channel MOSFETs turn on, no
additional power is generated for VCC2 (motor back-EMF
rectified through out the MOSFET body diodes). After
VCC2 drops below 4V, Q2 turns off. Continued braking
relies on the CGS of the N-Channel MOSFETs to sustain
the MOSFET gate enhancement voltage.
ML4411/ML4411A
60
50
40
30
20
10
0
0
0.01 0.02 0.03 0.04 0.05
COS
Figure 8. ILIMIT Output Off-Time vs. COS.
CDLY
VCC2
16K
POWER FAIL
17
+5
4.5K
VCC2 – 3V
UVLO
+ P3 ONLY
A6
–
RDLY
26
COMM. LOGIC
DIS PWR
VCC2
BRAKE
VCC2
+
2.1V
+
A5
–
1.4V
A4
–
COMMUTATION
LOGIC
8 DIS PWR
UVLO
27 ILIMIT
28 ICMD
12 ISENSE
AV = 5
A1
+
A3
–
Q
ONE
SHOT
+
–
A2
1K
P1 . . . P3
VCC
Q2
VCC2
CBRK
7
Q1
TRI-
ST.
B1
VIN
N1 . . . N3
RSENSE
COS 13
VCC
COTA 6
Figure 9. Current Control, Output Drive and Braking Circuits.
9
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