ML4827CS-1 View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
MFG CO.
'ML4827CS-1' PDF : 16 Pages View PDF
FUNCTIONAL DESCRIPTION (Continued)
The ML4827 should be locally bypassed with a 10nF and
a 1µF ceramic capacitor. In most applications, an
electrolytic capacitor of between 100µF and 330µF is also
required across the part, both for filtering and as part of
the start-up bootstrap circuitry.
LEADING/TRAILING MODULATION
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with
the modulating ramp. When the modulating ramp reaches
the level of the error amplifier output voltage, the switch
will be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the
ML4827
trailing edge modulation is determined during the ON
time of the switch. Figure 5 shows a typical trailing edge
control scheme.
In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation
is determined during the OFF time of the switch. Figure 6
shows a leading edge control scheme.
One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With
L1
I1
+
VIN
DC
SW2 I2 I3
I4
SW1
RL
C1
RAMP
REF +–EAU3
RAMP
OSC
CLK
U4
+
– U1
DFF
RQ
D U2
Q
CLK
VEAO
VSW1
TIME
TIME
Figure 5. Typical Trailing Edge Control Scheme.
L1
I1
+
VIN
DC
SW2 I2 I3
I4
SW1
C1 RL
RAMP
VEAO
+–EAU3
REF
RAMP
OSC
CLK
VEAO
+ CMP
– U1
U4
DFF
RQ
D U2
Q
CLK
VSW1
TIME
TIME
Figure 6. Typical Leading Edge Control Scheme.
13
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