ML6401CS-3 View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
MFG CO.
'ML6401CS-3' PDF : 10 Pages View PDF
ML6401
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER
CONDITIONS
Switching Characteristics
Maximum CLK Input Frequency
Clock Duty Cycle
CLK = 13.5MHz
tPWH
tPWL
Analog To Digital Converter Inputs — CLK
CLK ≤ 20MHz
CLK ≤ 20MHz
Low Level Input Voltage
VIL
High Level Input Voltage
Low Level Input Current
High Level Input Current
Input Capacitance
VIH
VIL = 0.1V
VIH = VDDD – 0.1V
Timing — Digital Outputs (CL = 15pF, IOL = 2mA, RL = 2kΩ, fCLK = 20MHz)
Sampling Delay
tDS
Output Hold Time
tHO
Output Delay Time
tDO
Three-State Delay Time — Output Enable
Three-State Delay Time — Output Disable
Analog To Digital Converter Outputs — Digital
Low Level Output Voltage
High Level Output Voltage
Output Current in Three-State Mode
IOL = 2mA
IOH = 2mA
Supplies
Analog, Digital & Output Supply Voltage
Analog Supply Current
Static
Digital Supply Current
fCLK = 20MHz
Output Supply Current
fCLK = 20MHz, CL = 0pF
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
TIMING DIAGRAM
N+2
N+1
SAMPLE
(VIN+) – (VIN–)
N
CLK
D0 TO D7
4
tDS
N–3
N–2
N–1
tHO
tDO
MIN
20
40
25
25
0
2.4
–5
–5
4
5
0
2.4
–20
4.5
TYP
MAX
UNITS
25
MHz
60
%
ns
ns
0.8
V
VDDD
V
+5
µA
+5
µA
4.0
pF
5
ns
12
10
ns
18
30
ns
10
25
ns
10
20
ns
0.6
V
VCCO
V
+20
µA
5.5
V
26
34
mA
10
15
mA
4
10
mA
N+3
N+4
N
OUT
tPWH
N+1
tPWL
Share Link: 
