ML6460 View Datasheet(PDF) - Micro Linear Corporation
Part Name
Description
MFG CO.
'ML6460' PDF : 30 Pages View PDF
ML6460
CLK
HSYNC
(output)
(0,0) or (0,1) or (1,0) or (1,1) via (SEL_HSYNC1, SEL_HSYNC0)
(0,0)
(0,1)
(1,0)
(1,1)
YCrCb BL
BL
BL
BL
BL
CB0
Y0
CR0
Y1
CB2
Y2
CR2
Y3
T
Beginning of Active Line
2T
3T
Selectable Delay Synchronization
Figure 4. Pixel Synchronization. For Master Mode, Active Edge at Beginning of Active Video.
(CBLANK = 1, SENSE_HSYNC = 0) (BL = Blanked Pixel)
CLK
HSYNC
(output)
(0,0) or (0,1) or (1,0) or (1,1) via (SEL_HSYNC1, SEL_HSYNC0)
(0,0)
(0,1)
(1,0)
(1,1)
YCrCb BL
BL
BL
BL
BL
CB0
Y0
CR0
Y1
CB2
Y2
CR2
Y3
T
Beginning of Active Line
2T
3T
Selectable Delay Synchronization (SEL_HSYNC1, SEL_HSYNC0)
Figure 4a. Pixel Synchronization. For Master Mode, Active Edge at Beginning of Active Video.
(CBLANK = 1, SENSE_HSYNC = 1) (BL = Blanked Pixel)
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